With the demand for memory devices having an ever-larger capacity and semiconductor devices having an ever-increasing data rate to be used in various electronic devices, semiconductor devices including a plurality of memory units, each memory unit having an independent input/output line, have been developed. In order to test each of the plurality of memory units in such a semiconductor device, test equipment is configured to provide test signals or data to input lines or data input/output lines of each memory unit. Accordingly, when testing the semiconductor device including the plurality of memory units, the test equipment uses as many pins as the result of multiplying the number of input lines included in each memory unit by the number of memory units. As a result, the test equipment requires a great amount of resources, i.e., pins, for the test, which may decrease the test efficiency. Thus, the resulting productivity of semiconductor devices including a plurality of memory units can also decrease.
Therefore, it is desired to reduce resources required by test equipment when operating in a test mode.